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Ordering number : ENA1180
LA74302FN
Overview
Monolithic Linear IC
Audio Interface for DSC
The LA74302FN is a SPEAKER AMP and MIC AMP built-in audio interface for DSC.
Functions
* Three-wire type SERIAL communications, MIC AMP * MIC power supply provided * ALC (ALC LEVEL: level changeover in three stages possible) * REC/PB LPF (fc=4kHz: 3rd order) * LINE output (with SERIAL MUTE) * SPEAKER AMP (compatible with BEEP input MIX) * With serial communications control electronic VOLUME
Specifications
Maximum Ratings at Ta=25C
Parameter Maximum supply voltage Allowable power dissipation Operating temperature Storage temperature Symbol VCC max Pd max Topr Tstg Ta85C * Conditions Ratings 5.0 500 -15 to +85 -55 to +150 Unit V mW C C
* Substrate mounting condition (30mm x 50mm x 0.8mm: glass epoxy) 2S2P
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
52808 TI IM 20060727-S00005 No.A1180-1/12
LA74302FN
Operating Conditions at Ta=25C
Parameter Recommended supply voltage Symbol VCCL VCCD VCCSP Allowable operating voltage range VCCL VCCD VCCSP Take care not to exceed Pd max. Conditions Ratings 3.0 3.0 3.0 2.7 to 3.6 2.7 to 3.6 2.7 to 3.6 Unit V V V V V V
Electrical Characteristics at Ta=25C, VCCL, D, SP=3.0V, f=1kHz
Parameter Circuit current Quiescent circuit current 1 Quiescent circuit current 2 Quiescent circuit current 3 Quiescent circuit current 4 Quiescent circuit current 5 Quiescent circuit current 6 REC output system REC reference output LEVEL REC reference output distortion rate 1 ALC characteristics 1 ALC distortion rate 1 ALC characteristics 2 ALC distortion rate 2 VOR HDR1 ALM1 ALMD1 ALM2 ALMD2 ALC IN, VIN=-44dBV ALC IN, VIN=-44dBV, THD: from 2nd to 5th harmonic ALC IN, VIN=-28dBV (reference+16dB), ALC LEVEL: reference +10dB ALC IN, VIN=-28dBV (reference +16dB), ALC LEVEL: reference +10dB ALC IN, VIN=-12dBV (reference +32dB), ALC LEVEL: reference +10dB ALC IN, VIN=-12dBV (reference +32dB), ALC LEVEL: reference +10dB, THD: from 2nd to 5th harmonic REC output noise voltage REC output frequency characteristics 1 REC output frequency characteristics 2 REC output frequency characteristics 3 LINE output system LINE reference output LEVEL LINE reference output distortion rate LINE reference output noise voltage LINE max output LEVEL LINE output frequency characteristics 1 LINE output frequency characteristics 2 LINE output frequency characteristics 3 VOL HDL VNOL VOML FEQP1 FEQP2 FEQP3 PB IN, VIN=-14dBV PB IN, VIN=-14dBV, THD: from 2nd to 5th harmonic PB IN, no input, JIS-A Filter PB IN, LEVEL at which THD (from 2nd to 5th harmonic)=1% PB IN, VIN=-10dBV, Comparison of f=4kHz/1kHz PB IN, VIN=-10dBV, Comparison of f=22kHz/1kHz PB IN, VIN=-10dBV, Comparison of f=100kHz/1kHz -1 -4.5 -7 -6 0.1 -90 0 -3 -31 -70 -1.5 -25 -60 -5 0.2 -82 dBV % dBV dBV dB dB dB VNOR FEQR1 FEQR2 FEQR3 ALC IN no input, JIS-A Filter ALC IN, VIN=-36dBV, Comparison of f=4kHz/1kHz ALC IN, VIN=-36dBV, Comparison of f=22kHz/1kHz ALC IN, VIN=-36dBV, Comparison of f=100kHz/1kHz -4.5 -82 -3 -31 -70 -68 -1.5 -25 -60 dBV dBV dB dB 0.4 1 % -7 -7 -15 -14 0.03 -4 0.3 -4 -13 0.1 -1 0.5 -1 dBV % dBV % dBV ICCA1 ICCA2 ICCA3 ICCD1 ICCSP1 ICCSP2 VCCA=3.0V: FULL operation VCCA=3.0V: REC BLOCK (MIC/ALC/REC AMP) POWER SAVE VCCA=3.0V: LINE AMP POWER SAVE VCCD=3.0V VCCSP=3.0V: SPK POWER ON VCCSP=3.0V: SPK POWER SAVE 5.2 2.4 4.8 2.1 1.2 0.3 7.0 3.2 6.4 2.8 2.5 0.6 8.8 4 8.0 3.5 5 0.9 mA mA mA mA mA mA Symbol Conditions Ratings min typ max Unit
Continued on next page.
No.A1180-2/12
LA74302FN
Continued from preceding page.
Parameter Symbol Conditions Ratings min typ max Unit
SP output system (SP load=as measured at 8 end) SP reference output LEVEL1 (Vol.MAX) SP reference output distortion rate SP reference output LEVEL2 (Vol.TYP) SP reference output LEVEL3 (Vol.MIN) SP reference output noise voltage SP max rated output MIC output system MIC voltage gain MIC output distortion rate MIC output noise voltage MIC max output LEVEL MIC VCC output voltage Control system Serial CLOCK frequency Serial input LOW level Serial input HIGH level FCLK SERLO SERHI 0 2.3 1.25 1.5 0.7 3.5 MHz V V VGMIC HDMIC VNOMIC VOMIC VMIC MIC IN, VIN=-40dBV MIC IN, VIN=-40dBV, THD: up to quintic MIC IN, no input, JIS-A Filter Output LEVEL at which THD=1% At 2.2k load -3 2.1 25 26 0.1 -91 -1 2.3 2.5 27 0.5 -83 dB % dBV dBV V VOSP1 THDSP VOSP2 VOSP3 VNOSP VOMSP PB IN, VIN=-14dBV, Vol=MAX (Serial DATA=31) PB IN, VIN=-14dBV, Vol=MAX, THD: from 2nd to 5th harmonic PB IN, VIN=-14dBV, Vol=TYP (Serial DATA=12) PB IN, VIN=-14dBV, Vol=MIN (Serial DATA=0), JIS-A Filter PB IN no input, Vol=MAX, JIS-A Filter PB IN, Vol=MAX, LEVEL at which THD=10% 150 -22 -8 -4 0.7 -16 -90 -86 250 0 1.5 -10 -70 -70 dBV % dBV dBV dBV mW
Package Dimensions
unit : mm (typ) 3292A
TOP VIEW SIDE VIEW BOTTOM VIEW (0.55) 5.0 (R0.3) (R0.2) 0.50 (0.2) 1.2 3 - Do Not Connect
5.0
0.95 0.5
0.95
0.5
12
21
28
Do Not Connect (1.0) 0.5
SIDE VIEW
0.2
0.0 NOM
(0.8)
0.85 MAX
SANYO : VQFN28J(5.0X5.0)
1.2
No.A1180-3/12
LA74302FN
Description of the Content of Serial Communication
DATA No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 REC BLOCK POWER SW LINE OUT POWER SW LINE MUTE SW SPK POWER SW DATA=1 DATA=2 DATA=4 DATA=8 DATA=16 * EVR setting (the numeral shown in the left is decimal. For characteristics, see P9.) DUMMY DUMMY DUMMY MIC AMP POWER SW ALC AMP POWER SW ALC LEVEL CTL 0: ON, 1: OFF 0: ON, 1: OFF +10dB: 0 +12dB: 1 0 0: ON, 1: OFF 0: ON, 1: OFF 0: ON, 1: OFF 0: ON, 1: OFF 1 1 1 1 1 : VOL MAX 0 0 0 0 0 : VOL MIN (MUTE) 0 +14dB: 0 1 Parameter Default 0 0 0 0 0 0 0 1 0 0 0 0 0
Serial Transmission Timing
VIH CS tCS CLOCK tDS DATA LSB MSB tDH VIH VIL fMAX tWH tWL tCH tWC VIH VIL VIL
* fMAX * tWL * tWH * tCS * tCH * tDS * tDH * tWC * VIH * VIL
(Max clock frequency) (Clock pulse width: Low) (Clock pulse width: High) (Chip enable setup time) (Chip enable hold time) (Data setup time) (Data hold time) (Chip enable pulse width) (High voltage lower limit) (Low voltage upper limit)
1.5MHz 333ns or more 333ns or more 333ns or more 333ns or more 333ns or more 333ns or more 333ns or more 2.3V to 3.5V 0V to 0.7V
No.A1180-4/12
LA74302FN
POWER ON Condition (SERIAL communication)
H
Power Supply
L
H Width of several hundreds NS POWER ON PULSE (Signal inside IC)
L
H
C.S.
L First DATA communication H POWER ON RESET (Singnal inside IC) Delay of several hundreds NS
L POWER ON RESET condition
SERIAL communication condition
First DATA hold
The POWER ON RESET condition continues up to the second C.S rising ( ) entered after falling ( ) of POWER ON PULSE ( ) generated inside IC at a time of power ON. Actually, because of delay of several hundreds NS in the IC, the first DATA condition begins in ( ) and the normal SERIAL communication condition begins after ( ).
No.A1180-5/12
LA74302FN
Electrical Characteristics Measurement Method at Ta=25C, VCCL, D, SP=3.0V, f=1kHz
Symbol Input Pin Conditions Pin Output Conditions 0 1 2 3 4 5 Serial control setting 6 7 8 9 10 11 12 13 14 15 Circuit current ICCA1 ICCA2 ICCA3 ICCS1 ICCS2 ICCD 12 12 12 26 26 10 VCCA=3.0V No input VCCA=3.0V No input VCCA=3.0V No input VCCSP=3.0V No input VCCSP=3.0V No input VCCD=3.0V No input REC output system VOR1 HDR 16 16 VIN=-44dBV f=1kHz VIN=-44dBV f=1kHz VIN=-28dBV f=1kHz VIN=-28dBV f=1kHz VIN=-12dBV f=1kHz VIN=-12dBV f=1kHz No input VIN=-36dBV f=4kHz VIN=-36dBV f=22kHz VIN=-36dBV f=100kHz VIN=-14dBV f=1kHz HDL 11 VIN=-14dBV f=1kHz No input f=1kHz 5 13 13 400 to 30kHz LPF used 400 to 30kHz LPF used THD: from 2nd to 5th harmonic ALM1 ALMD1 16 16 13 13 400 to 30kHz LPF used 400 to 30kHz LPF used THD: from 2nd to 5th harmonic ALM2 ALMD2 16 16 13 13 400 to 30kHz LPF used 400 to 30kHz LPF used THD: from 2nd to 5th harmonic VNOR FEQR1 FEQR2 FEQR3 16 16 16 16 13 13 13 13 JIS-A FILTER used f=4kHz/1kHz level ratio f=22kHz/1kHz level ratio f=100kHz/1kHz level ratio 5 400 to 30kHz LPF used 400 to 30kHz LPF used THD: from 2nd to 5th harmonic VNOL VOML 11 11 5 5 JIS-A FILTER used 400 to 30kHz LPF used Level at which THD = 1% (from 2nd to 5th harmonic) FEQP1 FEQP2 FEQP3 11 11 11 VIN=-10dBV f=4kHz VIN=-10dBV f=22kHz VIN=-10dBV f=100kHz VIN=-14dBV f=1kHz VIN=-14dBV f=1kHz 5 5 5 f=4kHz/1kHz level ratio f=22kHz/1kHz level ratio f=100kHz/1kHz level ratio 25 27 25 27 400 to 30kHz LPF used Vol.=MAX 400 to 30kHz LPF used Vol.=MAX, THD: from 2nd to 5th harmonic 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 12 12 26 26 10 FULL operation MIC/ALC/REC AMP POWER SAVE LINE AMP POWER SAVE FULL operation SPK AMP POWER SAVE FULL operation 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LINE output system VOL1 11 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
SPK output system (SPK end: measured with 8 ) VOSP1 THDSP 11 11 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
Continued on next page.
No.A1180-6/12
LA74302FN
Continued from preceding page.
Input Symbol Pi n VOSP2 VOSP3 11 11 Conditions Pin Output Conditions 0 1 2 3 4 5 Serial control setting 6 7 8 9 10 11 12 13 14 15
SPK output system (SPK end: measured with 8 ) VIN=-14dBV f=1kHz VIN=-14dBV f=1kHz No input f=1kHz 25 27 25 27 25 27 VOSSP 11 25 27 400 to 30kHz LPF used Vol.=TYP JIS-A FILTER used Vol.=MIN JIS-A FILTER used Vol.=MAX 400 to 30kHz LPF used Vol.=MAX, Level at which THD = 10% (from 2nd to 5th harmonic) MIC output system VGMIC HDMIC 21 21 Vin=-40dBV f=1kHz Vin=-40dBV f=1kHz VNOMIC VOMIC 21 21 No input f=1kHz 17 17 17 400 to 30kHz LPF used THD: from 2nd to 5th harmonic JIS-A FILTER used 400 to 30kHz LPF used Level at which THD=1% (from 2nd to 5th harmonic) VMIC 22 No input 22 Measure the output voltage at 2.2k load 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 400 to 30kHz LPF used 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0
SPK output system (SPK end: measured with 8 ) VNOSP 11 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
Description of Pin Functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Removal of speaker ripple Speaker input EVR output STANDBY control LINE output D GND C.S. input CLOCK input DATA input VCCD PB input VCCA REC output A GND ALC detection ALC input MIC output MIC Amp attenuator output MIC Amp NFB MIC GND MIC input INT power supply for MIC MIC Removal of ripple for VCC and VREFL SPK GND Speaker positive-phase output VCCSP Speaker negative-phase output SPK GND Pin Description
No.A1180-7/12
LA74302FN
LA74302FN BLOCK Diagram and Test Circuit Diagram
0.47F MIC IN 0.01F MIC GND MIC IN 21 20 MIC VCC 22 + 10F 24 25 8 VCCSP 3.0V SP GND 26 27 VREFS 28 1 10F +0.47 F 4.7 k 2 3 4 5 6 7 D GND LINE OUT LOGIC 8 CLOCK C.S MUTE 10 9 EVR LPF 23 MIC VCC VREFL + 12 11 0.47F VCCD 3.0V DATA 0.47F ALC IN + 19 18 17 16 ALC LPF 15 DET 14 13 A GND REC OUT VCCA 3.0V PB IN 4.7F
2.2k
0.1F
0.1F 4.7k STANDBY CTL:HIGH
LA74302FN EVR characteristics 0 -10 -20 EVR attenuation (dBV) -30 -40 -50 -60 -70 -80 -90 -100 0 5 10 15 20 25 30 Serial data set value (decimal) At input of PB IN = -9 dBV
No.A1180-8/12
LA74302FN
Table of Input/Output Forms of LA74302FN
PIN 1 Pin Name VREFS DC Voltage 1.25V AC Voltage Description of Functions Ripple removal pin Equivalent Circuit Diagram in Pin
VCCSP(=3.0V) 50k 1 500
35k
2
SP IN
1.25V
-10dBV (EVR MAX at PB reference input)
Speaker input pin
VCCSP(=3.0V) 400k 6.8k
27
SPK OUT-
1.25V
-10dBV (EVR MAX at PB reference input)
Speaker negative-phase output pin
2
27
3
EVR OUT
1.64V
-10dBV (EVR MAX at PB reference input)
EVR output pin
VCCA(=3.0V)
3
400
4
STANDBY H
STANDBY control pin 2V or more: STANDBY * Puts all amplifiers excluding speakers into the STANDBY state.
10k 4 60k
5
LINE OUT
1.50V
-6dBV (At PB reference input)
LINE output pin
VCCA(=3.0V)
5
5.7k
10k
VREF
6 7 D_GND CS 0V GND pin for serial communication block CS input pin
8
CLOCK
CLOCK input pin
7 8
500
9
DATA
DATA input pin
9
Continued on next page.
No.A1180-9/12
LA74302FN
Continued from preceding page.
PIN 10 Pin Name VCCD DC Voltage 3.0V AC Voltage Description of Functions Power pin for driving of the serial communication block and all amplifier starter circuits 11 PB IN 1.64V -14dBV (Reference input level) PB input pin Equivalent Circuit Diagram in Pin
VCCA(=3.0V)
11
500
50k
VREFL
12 13 VCCA REC OUT 3.0V 1.50V -14dBV (At MIC reference input) Analog signal block power pin REC output pin
VCCA(=3.0V)
13
9k
5.1k VREF
14 15 A GND ALC DET 0V Analog signal block GND pin ALC detection pin
VCCA(=3.0V)
1k 15 500
16
ALC IN
1.64V
-44dBV (At MIC reference input/output)
ALC input pin
VCCA(=3.0V)
16
500
50k
VREF
17 MIC OUT 1.64V -44dBV (At MIC reference input) MIC output pin
VCCA(=3.0V)
17
500
10.7k
3.8k
VREF Continued on next page.
No.A1180-10/12
LA74302FN
Continued from preceding page.
PIN 18 Pin Name MIC ATT DC Voltage 0.30V AC Voltage Description of Functions MIC Amp attenuator output pin Equivalent Circuit Diagram in Pin
VCCA(=3.0V)
19
MIC NFB
1.64V
MIC Amp NFB pin
4.3 k 18 950
100k
300
19
20 21
MIC GND MIC IN
0V 1.64V -70dBV (Reference input level)
MIC Amp block GND pin MIC input pin
VCCA(=3.0V)
21
500
70k VREFL
22 MIC VCC 2.30V MIC power pin
VCCA(=3.0V) 100
22
500 20k
23
VREFL
2.30V
MIC VCC and VREFL ripple removal pin
VCCA(=3.0V) 13k 23 12.4k 30.7k
24 28 25
SP GND SPK OUT+
0V 1.25V -10dBV (EVR MAX at PB reference input)
Speaker GND pin Speaker positive-phase output pin
VCCSP(=3.0V)
25
5.1k 5k 27
26
VCCSP
3.0V
Speaker power pin
No.A1180-11/12
LA74302FN
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above.
This catalog provides information as of May, 2008. Specifications and information herein are subject to change without notice.
PS No.A1180-12/12

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